library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity tb_parametric_register is
end entity tb_parametric_register;

architecture BEH of tb_parametric_register is
    constant NUM_BIT : natural := 8;
    signal clk   : std_logic := '0';
    signal rst   : std_logic := '0';
    signal en    : std_logic := '0';
    signal inputs : std_logic_vector(NUM_BIT-1 downto 0) := (others => '0');
    signal outputs : std_logic_vector(NUM_BIT-1 downto 0);

    component parametric_register is
        generic (
            NUM_BIT : natural := 8
        );
        port (
            clk : in std_logic;
            rst : in std_logic;
            en : in std_logic;
            inputs : in std_logic_vector(NUM_BIT-1 downto 0);
            outputs : out std_logic_vector(NUM_BIT-1 downto 0)
        );
    end component;

begin
    dut : parametric_register
        generic map (
            NUM_BIT => NUM_BIT
        )
        port map (
            clk => clk,
            rst => rst,
            en => en,
            inputs => inputs,
            outputs => outputs
        );

    clk_process : process
    begin
        clk <= not clk;
        wait for 10 ns;
    end process;

    stim_process : process
    begin
        wait for 10 ns; -- инициализация
        rst <= '1'; -- сброс
        wait for 10 ns;
        rst <= '0';

        -- Тестирование записи
        en <= '1';
        inputs <= "10101010";
        wait for 10 ns;
        assert outputs = "10101010" report "Error read";

        -- Тестирование сброса
        rst <= '1';
        wait for 10 ns;
        assert outputs = "00000000" report "Error reset";
		rst <= '0';

        -- Тестирование блокировки записи
        en <= '0';
        inputs <= "11001100";
        wait for 20 ns;
        assert outputs = "00000000" report "Error block";
		en <= '1';

        wait;
    end process;
end architecture BEH;